The present invention generally relates to the implementation of tunable delay lines. More specifically, the present invention relates to the implementation of tunable delay lines which can be used to reduce electromagnetic interference generated by the clock and other signals inside electronic devices such as computers and cellular telephones.
The electromagnetic interference (EMI) generated by an electronic device must be suppressed to avoid interference with other electronic devices and to satisfy FCC regulations. For example, a number of computer workstations or servers contain conductive components in their cases or housings to create Faraday cages to limit the emissions of EMI. The incorporation of such components to provide shielding of EMI adds to the cost of manufacturing the workstations and servers.
The clock signal is the dominant source of EMI for many electronic devices. In addition, since the currents flowing through the power and data paths for an integrated circuit tend to be temporally correlated with the clock signal, other signals which bear a relationship with the clock signal can also be a source of EMI within an electronic device.
Most of the energy causing EMI is radiated via the power supply signals on the circuit board and in the IC package. Because the clock signal is generally periodic, much of this radiation is concentrated at the clock frequency and its harmonics. In other words, when the energy spectrum of the clock signal is shown graphically, there are distinctive peaks associated with certain frequencies.
One way to mitigate the effects of this radiation is to modulate the clock signal so that the energy is spread over a wider range of frequencies. This can reduce the severity of the interference caused by the electronic device as most radio communications devices operate with relatively narrow band signals. As a result, FCC regulations for EMI specify a maximum intensity in any small band of the spectrum.
Since the clock signal is an important component of any computer, the opportunity to utilize spread spectrum clock generators has been exploited in some PC designs. Frequency modulation has been used to provide a spread energy spectrum. For example, NeoMagic Corporation sells a reference clock generator where the reference oscillator is frequency modulated by a triangular wave with a frequency near 50 MHz (see Dual-Loop Spread-Spectrum Clock Generator, Proceedings of the 1999 IEEE International Solid-State Circuits Conference, pp. 184–185, 459, February, 1999). Intel has committed to support this approach which means that it is guaranteed that Intel's on-chip phase-locked loops will operate properly when driven by such a frequency modulated source.
FIG. 1 shows a typical clock generator for a CPU. A reference oscillator 10 generates a stable clock signal which is multiplied in frequency by a phase-locked loop 12 on the CPU chip 14 to obtain the CPU clock. Typically, the frequency multiplication is in the range of two to six. The high frequency signal from the phase-locked loop 12 is then amplified by a clock buffer 16 and accordingly distributed to the logic circuitry 18 outside of the CPU 14.
However, the primary objectives of phase-locked loop (PLL) design are in opposition to the goals of frequency modulations. In particular, the on-chip PLL is generally designed to be as stable as possible to minimize clock jitter. Thus, it is desirable to use a low-pass filter in the PLL with the lowest cut-off frequency possible. On the other hand, for the frequency modulation technique to be effective, the cut-off frequency of the low-pass filter must be higher than the modulation frequency. In addition to compromising clock jitter, this trade-off limits the modulation frequency for the reference. When low modulation frequencies are used, the computer may still produce noxious EMI even if it technically satisfies the FCC requirements. For this reason, some computer manufacturers have expressed reluctance to utilize the frequency modulation technique to achieve a wide energy spectrum clock.
Using frequency modulation to generate a wider energy spectrum for a clock signal has a number of additional disadvantages. For example, frequency modulation affects the operation of the PLL 12. Hence, the stability of the PLL 12 is affected. Moreover, the energy spreading resulted from using frequency modulation generally takes relatively longer periods of time to achieve. In the related U.S. patent application Ser. No. (to be assigned), entitled EMI REDUCTION USING TUNABLE DELAY LINES, concurrently filed and commonly assigned, an apparatus and method using tunable delay lines to reduce electromagnetic interference generated by signals inside electronic devices is described. The present invention described herein provides further details regarding the implementation of tunable delay lines to permit electromagnetic interference reduction. In addition to the foregoing, it is commonly known that there are various other applications of tunable delay lines.